Welcome to FPGAworld Conference 2019 in
Stockholm 17 September and Copenhagen 19 September
The FPGAworld Conference is an international forum for researchers, engineers, teachers, students and hackers. It covers topics such as complex analog/digital/software FPGA SoC systems, FPGA/ASIC based products, educational & industrial cases and more. Registration for attendees is free and includes coffee and lunch.
Download programs (coming)
Keynote Speakers Copenhagen
Keynote speaker: Jens Stapelfeldt, Xilinx
Title: Did Europe miss the start in AI Technology?
Abstract: What does the Scandinavian AI landscape look like in comparison to other European and international countries, in which areas is progress already being made, and what can be done tomorrow?
Artificial Intelligence (AI) has been the megatrend in the technology world for several years now. This talk gives a short overview of the AI/ML (machine learning) landscape and where Scandinavia stands in comparison. One trend in AI technology is the integration of AI in “Edge” Devices, i.e. in the device on site! One focus of the talk is to show what is possible today with optimized CNN networks and what we can expect in the next generation. We will also discuss “how do we get 20TFOLP into an SSD network under 10W to run without going into the cloud and consuming hundreds of Watts”?
Keynote speaker: David Clarke, Intel PSG
Title: FPGA, the mainstream accelerator of choice for the FinTech Industry
Abstract: The increase in the requirement for greater levels of compute density driven by increasing regulatory pressure is critically driving the need for acceleration in the financial data-centers. For a many year’s, CPU’s have been the preferred processing engine because of their programmability and their faster implementation of algorithms. With the increased need for deterministic latency, near real-time option price and trends calculations the ultra-flexible FPGA is becoming the most efficient acceleration processing platform in Fintech. Alternative technologies such as GPU, struggle to deliver the performance, power and usability required to scale as an accelerator across data-center.
The presentation focus on how the barriers is removed paving the way for adoption of FPGA in FSI (Financial Service Industry) by developing high level abstraction financial libraries and frameworks to allow fast time-to-market development of OpenCL/HLS algorithms. The FPGA is becoming the mainstream accelerator in the FSI data-centers.
CV: David Clarke has experience in Business Development Manager, Financial Acceleration and Fintech, EMEA at Intel Corporation and long experience within the FPGA and applications in Fintech. More information: https://www.linkedin.com/in/david-clarke-a4b04b2/
Keynote Speakers Stockholm
Keynote speaker: David Thomas, Intel PSG
Title: Where do FPGA’s outperform GPU’s
Abstract: David Thomas will talk about the big picture and market segments where FPGA based acceleration plays at its best! Is all about TCO (Total Cost of Ownership), Performance/Watt ratio’s from the Edge to the Datacenter (and back).
The latency, power efficiency and ability to handle various workloads will be the critical parameters defining the HW choices of our Users/customers. In addition to having an agnostic, high level SW tool.
CV: David Thomas started his career in 1996 as a Field Application Engineer for Altera within the distribution channel in Belgium. In 2000, he founded his own representative company in Benelux. In 2014, he joined Altera as Sales Manager Benelux to then moved to Munich in June’2015 to become the Area Sales Director of Altera for Central Europe (focus : Industrial, Automotive, ‘DataCentric’-Applications).
Since January’19, David is responsible for the EMEA PSG Channel partners.
More information: https://www.linkedin.com/in/david-thomas-838568/
Keynote speaker: Joe Mallett, Synopsys Inc.
Title: Build and Debug Highly Reliably FPGA-based Designs
Abstract: In today’s complex FPGA designs there is a need to integrate an ability to most effectively and economically deploy SEU mitigation and error monitoring circuitry in their FPGA-based systems targeting high radiation environments. In the overall design of a system, there is an opportunity to take advantage of triple modular redundancy (TMR) for creating an error detection and mitigation scheme. Important considerations include area and power increase, which affect system cost and can in some cases increase the probability of an SEU and the overall design performance challenges when applying the techniques. This presentation discusses the debug of these mitigation techniques available for different types of FPGAs. Also, the talk is about how complete some simple testing of voter logic and triplicates within the error detection and correction schemes. The combined capability of debug and fault injection allow developers to easily see each triplication and voter to verify and monitor whether the SEU mitigation techniques are working as expected. The last part is a discussion of future development to build highly reliably FPGA- based design.
CV: Joe Mallett has 20 years of experience in design and implementation in the semiconductor and EDA industries. Before joining Synopsys he was a Senior Product Marketing Manager at Xilinx Semiconductor where he worked to define and launch FPGA products. His background includes SoC design/prototyping, embedded software, HDL Synthesis, IP, and Product/Segment Marketing. He holds a BSEE from Portland State University.
Sponsor, Exhibitors and Presenters
Copenhagen and Stockholm