Welcome to FPGAworld Conference 2018 in
Stockholm 18 September and Copenhagen 20 September
The FPGAworld Conference is an international forum for researchers, engineers, teachers, students and hackers. It covers topics such as complex analog/digital/software FPGA SoC systems, FPGA/ASIC based products, educational & industrial cases and more. The academic & industrial tracks at FPGAworld, meals, premises, administration etc. is paid for by industry sponsors and exhibitors.
Keynote Speaker 2018, Stockholm and Copenhagen
Keynote speaker: Pieter J. Hazewindus, Synopsys, Mountain View, CA
Title: Advanced Verification and Debug for Large and Complex FPGA Designs
Abstract: The FPGA industry is in a period of rapid change. There has been a significant growth in size and complexity of FPGAs with each new generation. This has given rise to several challenges to FPGA design which are now needing a more ASIC “like” design methodology. We survey the implications for designers implementing FPGAs, IP designers, as well as the tools supporting the FPGA designs.
With the introduction of FinFET technology-based FPGAs, single-FPGA design sizes have taken a big leap, while the maximum operating frequencies have increased, and the power consumption has decreased dramatically. FPGAs have become more feasible as replacements for ASICs, and as stepping stones towards eventual ASIC implementations. The scale of integration challenges traditional testing methods, such as simulation. More complex clocking schemes require enhanced verification methodologies. And RTL debug of a multi-million gate FPGA design in reasonable time necessitates novel strategies.
Pieter Hazewindus leads the development of software solutions for the implementation of FPGA designs as well as ASIC prototyping on FPGAs at Synopsys. He is responsible for the Synplify Pro and Premier family of products, which have provided synthesis support for FPGA vendors since 1994. Prior to Synopsys, he held both managerial and software developer positions at Synplicity, Cogit Corporation, and Mentor Graphics. Hazewindus holds a Ph.D. in Computer Science from the California Institute of Technology and an M.S. in Mathematics from the Eindhoven University of Technology. More; https://www.linkedin.com/in/graham-copperwheat-5991755/
Keynote Speakers 2018, Stockholm
Keynote speaker: Graham Copperwheat – Intel PSG located in UK.
Title: FPGA – The Multifunction Accelerator of ChoicePGA
Abstract: Recently, we’re living in an increasingly smart and connected world, a world that is generating increasing amounts of data and driven to find new ways to extract value from this data. A world that needs technology solutions that can not only meet today’s demands but also tomorrows. FPGAs are stepping up to meet this challenge by writing the next chapter in the story of their evolution – FPGA as a reconfigurable multifunction accelerator. What are the characteristics of this new chapter, what are the strategies the FPGA industry is deploying to address the demand?
More about Graham Copperwheat see: https://www.linkedin.com/in/graham-copperwheat-5991755/
Keynote Speakers 2018, Copenhagen
Keynote speaker: Hichem Belhadj, Chief Systems Architect – CTO Office, Microsemi Corp. USA
Title: Artificial Intelligence and the Use of Programmable Technologies
Abstract: Recently, Artificial Intelligence (AI) went from hype to become reality as platforms and eco-systems that incorporate artificial intelligence gain ground in many sectors such as Ad targeting and E-commerce, traffic and network analytics, Insight-driven financial transaction, clinical analytics, and autonomous factories. In this keynote, we will review the underlying hardware and eco-system architectures enabling machine learning, cognitive computing and other advanced analytics technologies. A review of the various hardware processing capabilities (GPUs, CPUs, FPGAs) and how they are pooled and harnessed broadly to accelerate computational workloads. The review will also cover the much-needed eco-system to enable many more applications and a broader community of users. At the end, we will introduce an exploration of which architecture fits what workload.
Hichem Belhadj has been with Microsemi for close to 20 years. He is currently the Chief System Architect at the CTO Office. Prior to joining the CTO Office, Hichem held executive management positions in Corporate Sales and Field Systems and Applications at Microsemi, Actel, IST, and INPG. Hichem holds a Master and PhD from the Polytechnic Institute of Grenoble, France. More; https://www.linkedin.com/in/hichem-belhadj-43b6792/
Title: VUnit 3 – Develop Code with Confidence and Speed (90 min, Stockholm)
VUnit (vunit.github.io) is an open source testing framework for VHDL and SystemVerilog founded in 2014 by Lars Asplund from Synective Labs and Olof Kraigher from Veoneer. It features the functionality needed to realize continuous and fully automated testing of your HDL code. (more information in the abstract)
2018 Sponsors (updates)
2018 Exhibitors and Presenters
Copenhagen and Stockholm
DTU, Technical University of Denmark
Aktuel Elektronik, Denmark
Dini Group, USA
Intel PSG, USA
Avnet Silica, Denmark
Avnet Silica, Sweden
Synective Labs, Sweden