2019: Program for Stockholm and Copenhagen
Keynote Speakers Copenhagen
Keynote speaker: Jens Stapelfeldt, Xilinx
Title: Did Europe miss the start in AI Technology?
Abstract: What does the Scandinavian AI landscape look like in comparison to other European and international countries, in which areas is progress already being made, and what can be done tomorrow?
Artificial Intelligence (AI) has been the megatrend in the technology world for several years now. This talk gives a short overview of the AI/ML (machine learning) landscape and where Scandinavia stands in comparison. One trend in AI technology is the integration of AI in “Edge” Devices, i.e. in the device on site! One focus of the talk is to show what is possible today with optimized CNN networks and what we can expect in the next generation. We will also discuss “how do we get 20TFOLP into an SSD network under 10W to run without going into the cloud and consuming hundreds of Watts”?
Keynote speaker: David Clarke, Intel PSG
Title: FPGA, the mainstream accelerator of choice for the FinTech Industry
Abstract: The increase in the requirement for greater levels of compute density driven by increasing regulatory pressure is critically driving the need for acceleration in the financial data-centers. For a many year’s, CPU’s have been the preferred processing engine because of their programmability and their faster implementation of algorithms. With the increased need for deterministic latency, near real-time option price and trends calculations the ultra-flexible FPGA is becoming the most efficient acceleration processing platform in Fintech. Alternative technologies such as GPU, struggle to deliver the performance, power and usability required to scale as an accelerator across data-center.
The presentation focus on how the barriers is removed paving the way for adoption of FPGA in FSI (Financial Service Industry) by developing high level abstraction financial libraries and frameworks to allow fast time-to-market development of OpenCL/HLS algorithms. The FPGA is becoming the mainstream accelerator in the FSI data-centers.
CV: David Clarke has experience in Business Development Manager, Financial Acceleration and Fintech, EMEA at Intel Corporation and long experience within the FPGA and applications in Fintech. More information: https://www.linkedin.com/in/david-clarke-a4b04b2/
Keynote Speakers Stockholm
Keynote speaker: David Thomas, Intel PSG
Title: Where do FPGA’s outperform GPU’s
Abstract: David Thomas will talk about the big picture and market segments where FPGA based acceleration plays at its best! Is all about TCO (Total Cost of Ownership), Performance/Watt ratio’s from the Edge to the Datacenter (and back).
The latency, power efficiency and ability to handle various workloads will be the critical parameters defining the HW choices of our Users/customers. In addition to having an agnostic, high level SW tool.
CV: David Thomas started his career in 1996 as a Field Application Engineer for Altera within the distribution channel in Belgium. In 2000, he founded his own representative company in Benelux. In 2014, he joined Altera as Sales Manager Benelux to then moved to Munich in June’2015 to become the Area Sales Director of Altera for Central Europe (focus : Industrial, Automotive, ‘DataCentric’-Applications).
Since January’19, David is responsible for the EMEA PSG Channel partners.
More information: https://www.linkedin.com/in/david-thomas-838568/
Keynote speaker: Madhav Chikodikar, Director of R&D, Synopsys, Inc.
Title: Build and Debug Highly Reliably FPGA-based Designs
Abstract: In today’s complex FPGA designs there is a need to integrate an ability to most effectively and economically deploy SEU mitigation and error monitoring circuitry in their FPGA-based systems targeting high radiation environments. In the overall design of a system, there is an opportunity to take advantage of triple modular redundancy (TMR) for creating an error detection and mitigation scheme. Important considerations include area and power increase, which affect system cost and can in some cases increase the probability of an SEU and the overall design performance challenges when applying the techniques. This presentation discusses the debug of these mitigation techniques available for different types of FPGAs. Also, the talk is about how complete some simple testing of voter logic and triplicates within the error detection and correction schemes. The combined capability of debug and fault injection allow developers to easily see each triplication and voter to verify and monitor whether the SEU mitigation techniques are working as expected. The last part is a discussion of future development to build highly reliably FPGA- based design.
CV: Madhav Chikodikar is Director of R&D with the FPGA software group at Synopsys, India. He has been working in the area of logic synthesis for FPGAs and ASICs for last 25 years. Madhav leads a team working on development of Synplify Premier and HAPS ProtoCompiler products. Prior to Synopsys, Madhav worked with Synplicity and SASKEN. Madhav‘s background includes logic synthesis and optimizations, timing analysis, ASIC prototyping and high reliability designs using FPGAs. Madhav is a senior member of IEEE.
Sponsor, Exhibitors and Presenters
Copenhagen and Stockholm
Bitvis and CGI, Norway
Silicon Labs, Finland
Synective Labs, Sweden
Blue Pearl Software Inc, USA
Motion Control, SwedenAGSTU FPGA Education (Yrkeshögskola), Sweden
2018: Stockholm 18 September and Copenhagen 20 September
The FPGAworld Conference is an international forum for researchers, engineers, teachers, students and hackers. It covers topics such as complex analog/digital/software FPGA SoC systems, FPGA/ASIC based products, educational & industrial cases and more. The academic & industrial tracks at FPGAworld, meals, premises, administration etc. is paid for by industry sponsors and exhibitors.
Keynote Speaker, Stockholm and Copenhagen
Keynote speaker: Pieter J. Hazewindus, Synopsys, Mountain View, CA
Title: Advanced Verification and Debug for Large and Complex FPGA Designs
Abstract: The FPGA industry is in a period of rapid change. There has been a significant growth in size and complexity of FPGAs with each new generation. This has given rise to several challenges to FPGA design which are now needing a more ASIC “like” design methodology. We survey the implications for designers implementing FPGAs, IP designers, as well as the tools supporting the FPGA designs.
With the introduction of FinFET technology-based FPGAs, single-FPGA design sizes have taken a big leap, while the maximum operating frequencies have increased, and the power consumption has decreased dramatically. FPGAs have become more feasible as replacements for ASICs, and as stepping stones towards eventual ASIC implementations. The scale of integration challenges traditional testing methods, such as simulation. More complex clocking schemes require enhanced verification methodologies. And RTL debug of a multi-million gate FPGA design in reasonable time necessitates novel strategies.
Pieter Hazewindus leads the development of software solutions for the implementation of FPGA designs as well as ASIC prototyping on FPGAs at Synopsys. He is responsible for the Synplify Pro and Premier family of products, which have provided synthesis support for FPGA vendors since 1994. Prior to Synopsys, he held both managerial and software developer positions at Synplicity, Cogit Corporation, and Mentor Graphics. Hazewindus holds a Ph.D. in Computer Science from the California Institute of Technology and an M.S. in Mathematics from the Eindhoven University of Technology. More; https://www.linkedin.com/in/graham-copperwheat-5991755/
Keynote Speakers, Stockholm
Keynote speaker: Graham Copperwheat – Intel PSG located in UK.
Title: FPGA – The Multifunction Accelerator of ChoicePGA
Abstract: Recently, we’re living in an increasingly smart and connected world, a world that is generating increasing amounts of data and driven to find new ways to extract value from this data. A world that needs technology solutions that can not only meet today’s demands but also tomorrows. FPGAs are stepping up to meet this challenge by writing the next chapter in the story of their evolution – FPGA as a reconfigurable multifunction accelerator. What are the characteristics of this new chapter, what are the strategies the FPGA industry is deploying to address the demand?
More about Graham Copperwheat see: https://www.linkedin.com/in/graham-copperwheat-5991755/
Flyover Cabling Solutions for High Performance Interconnect for FPGAs (Stockholm)
Open for registration
Two compulsory registrations: send e-mail to Kevin.Burt@samtec.com and registration on the FPGAworld (max 12 persons).
As FPGA speeds increase to 56/112 Gbps PAM4, and the number of transceivers increase, so do the system design challenges. Signal integrity, thermal and packaging considerations place extreme constraints on the entire path out of the FPGA.
Traditional PCB routings are limited by the material resulting in shorter traces or more expensive exotic materials and layout challenges getting all the 56/112 G signals routed. As a result, the Interconnect Industry has created flyover cable solutions to enable these high bandwidth, high density links. These flyover solutions enable improved Signal integrity, low system power, and high performance, high density FPGA connections by taking the high speed signals off board and into low loss cables.
In this tutorial, you will learn the challenges of using traditional PCB layout techniques as well as the advantages of copper and optical cables as well as the system advantages that they enable.”
Exhibitors and Presenters
Copenhagen and Stockholm
DTU, Technical University of Denmark
Aktuel Elektronik, Denmark
Dini Group, USA
Intel PSG, USA
Avnet Silica, Denmark
Avnet Silica, Sweden
Synective Labs, Sweden
Trenz Electronic, Germany
2017: Stockholm 19 September and Copenhagen 21 September
Keynote Speaker 2017, Copenhagen
Keynote speaker: Hans Holten-Lund, Prevas AB
Title: Acceleration of Convolutional Neural Networks in FPGAs
Abstract: The keynote presentation will discuss some of the issues we face as FPGA designers when tasked with the computational loads involved in signal processing. New tools are appearing, aiming at making it easier to design signal processing blocks. Convolutional Neural Networks share many techniques with more traditional signal processing. Explore tradeoffs, design-time vs performance. Floating-point vs fixed-point math. GPUs vs FPGAs.
Hans Holten-Lund is a Senior FPGA Designer at Prevas, and has a Ph.D. and M.Sc. EE from IMM, Technical University of Denmark. He has worked mainly on FPGA design for phased array ultrasound scanners, and and other embedded FPGA based systems, including computer vision. Also has industry experience with multi-gigabit networks and 3D computer graphics. A longer CV is available here: https://www.linkedin.com/in/hans-holten-lund-a3a53114/
Keynote Speakers 2017, Stockholm
Keynote speaker: Brendan Farley, XILINX Inc.
Title: RF Data Converters in an All Programmable MPSoC FPGA
Abstract: Recent state-of-the-art FPGAs have seen the integration of multi-giga-sample RF data converters to address the requirements of next generation wideband digital communications system. The keynote presentation will give an overview of the RFSoC FPGA which integrates such functionality and will discuss some potential applications and future trends
Brendan Farley is a Senior Director of Engineering at US multinational technology corporation Xilinx Inc. where he is responsible for Analog and Digital-RF Research and Development. Brendan holds a Bachelor Degree in Electronic Engineering from Trinity College Dublin and a Master of Science Degree in Technology Management from NUI Galway.
Keynote speaker: Hichem Belhadj, Chief Systems Architect – CTO Office, Microsemi Corp. USA
Title: Programmable Technologies: New Challenges and New Opportunities
Abstract; More to come
Hichem Belhadj has been with Microsemi for close to 20 years. He is currently the Chief System Architect at the CTO Office. Prior to joining the CTO Office, Hichem held executive management positions in Corporate Sales and Field Systems and Applications at Microsemi, Actel, IST, and INPG. Hichem holds a Master and PhD from the Polytechnic Institute of Grenoble, France.
Thanks to the sponsors:
Exhibitors and Presenters
Copenhagen and Stockholm
2016 Stockholm 13 September
Keynote Speakers 2016 Stockholm
Keynote speaker: Frank Förster, VP EMEA, Intel PSG.
Frank Förster is with Intel Programmable Solutions Group (formerly Altera) since 2007 in several positions. Prior to Altera, Frank Förster was working for companies in the field of Industrial Automation, Automotive as well as Digital Signal Processing. Frank Förster holds an engineering degree in EE/telecommunication.
Title: The Impact of Semiconductor Trends on future FPGA platforms
Abstract: This talk will first discuss semiconductor industry trends, then it will outline the profound implication the trends will have on future FPGA platforms across multiple vertical segments.
Keynote speaker: Mike Dini
Title: FPGAs — A Report from the Trenches
Mike Dini, an old FPGA veteran, will present his view of the present state of the FPGA industry. He will address the past, present, and future of the FPGA world.
2015 Stockholm 8 September and Copenhagen 10 September
Program with more information
Keynote Speakers 2015 Copenhagen, Professor Vincent Mooney III, Georgia Institute of Technology, Atlanta, USA
Title: Hardware Security and FPGAs: Strategies and Counterattacks
Recent highly publicized security attacks on businesses and governments have heightened the awareness of hardware vulnerability to malicious attacks. FPGA technology offers a unique strategy not available to application-specific non-programmable hardware: reconfiguration. This talk will give an overview of recent results in hardware security including an approach based on hardware signatures. The ability of hardware reconfiguration to protect run-time hardware and software highlights the advantages of FPGAs.
Keynote Speakers 2015 Stockholm, Professor Ahmed Hemani, Dept. of Electronics and Embedded Systems, School of ICT, KTH, Sweden
Title: Next Generation Massively Parallel VLSI Architectures and Design Methods
ITRS for the mobile category has challenged the VLSI Design community to come up with solutions by 2020 to provide 1000X improvement in performance with 120% increase in power budget and no increase in the design team size to cope with a 10X increase in design complexity. We propose a solution based on Coarse Grain Reconfigurable Fabric for computation and storage called DRRA – Dynamically Reconfigurable Resource Array. This fabric provides a near ASIC performance and yet retains programmability. This fabric enables dataflow graphs along with their control to be implemented in arbitrary degree of parallelism in a true hardware fashion. The DRRA fabric also comes with a novel System-level to GDSII design flow based on a concept called SiLego. SiLego is based on a grid based design and use of large grain building blocks called SiLego instead of the prevalent standard cells. The SiLego blocks snap fit to compose a GDSII macro and provide a predictable micro-architecture level physical design target to empower true high-level and system-level syntheses.
Sponsors, Exhibitors and Product Presenters
Exostiv Labs, Belgium
Linear Technology, USA
The Dini Group, USA
Synective Labs, Sweden
Microsemi , USA
Arrow Electronics, USA
ELMATICA AS, Norway
AGSTU AB, Sweden
Keynote Speakers 2014 Hichem Belhadj, Microsemi Corp, USA
Title: Field Programmable SoCs: The Greatest Acceleration of the Innovation Race
Short Biography: Hichem Belhadj has been involved in the Programmable Logic Industry since the late 80s. He has been with Microsemi SoC (former Actel) for over 15 years. Hichem has recently moved to Microsemi Corporate to lead the Field Systems and Applications Engineering. He holds a Master and a PhD from the Polytechnic Institute of Grenoble.
Keynote Speakers 2013:
- Jonas Nilsson, Synopsys, USA. Title: Programmable Platform – The Cornerstone of Verification
- Mike Dini, Dini Group, USA. Title: FPGAs – Past, present, and Future. Notes from the past 25 years
- Prof. Koen Bertels, Technical University of Delft, Netherland. Title: From FPGA to Polymorphic computing
Keynote Speakers 2012:
- Göran Bilski, Xilinx. Title: Heterogeneous computing in FPGAs
- Dr. Pieter Hazewindus, Synopsys, USA. Title: Managing FPGA design complexity: a software perspective
- Mike Woodward, MathWorks. Title: Model-Based Design for FPGAs – Fact or Fiction?